Data buses are used in integrated circuits (ICs) to transfer data between master devices, such as user-controlled microprocessors, and slave devices controlling peripheral devices, such as memories or the like. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA) bus. The AHB bus provides high performance, high clock frequency data transfer between multiple bus master devices and multiple bus slave devices through use of an arbiter. The AHB bus is particularly useful in integrated circuit chips, including single chip processors, to couple processors to on-chip memories and to off-chip external memory interfaces.
The AHB bus is a pipelined bus that operates in two phases, a command phase followed by a data transfer phase. The master device instructs, or commands, the slave device during the command phase to perform a specific type of data transaction, and the slave device transfers data with the master device during the data transfer phase. For example, a read command will command the slave to read data from its storage device during the command phase and transfer that data to the master device via the bus during the data transfer phase.
The operating frequency of the peripheral device is not always the same as that of the data bus and slave device. Consequently, the slave device ordinarily includes first-in, first-out (FIFO) registers that buffer commands and data across the frequency barrier. The commands are received by an input register which supplies commands to an input command FIFO, which in turn supplies commands to the device controller of the peripheral device.
FIFOs embodied in ICs require a considerable amount of chip area; the physical size of the FIFO is proportional to the maximum number and size of words held by the FIFO. To minimize the size of the FIFO, and hence the chip size, it is desirable to minimize the maximum number of words to be held by the FIFO. In the case of the input command FIFO, it is desirable to minimize the number of commands held by the FIFO.
In a read operation, the device controller will pull the read command from the command FIFO and execute the command. Consequently, a large command FIFO is not required for read operations. However, in a write operation, the data being written may be voluminous, extending over several data beats (cycles). The device controller pulls the write command from the command FIFO to write each beat of write date to the memory or other device.
In the AHB bus, a write command, which includes an address of the peripheral device to which data are to be written, is associated with each beat of data in a multi-beat write data transfer. The slave device inserts each write command into the command FIFO. Consequently, the command FIFO must contain a number of commands corresponding to the number of beats of write data. If the data burst contains four beats of data, the command FIFO holds four commands; if the data burst contains sixteen beats, the command FIFO holds sixteen commands. However, this solution requires a large command FIFO to accommodate the multiple write commands, which requires a considerable amount of area on the integrated chip.